Spacer defined fin growth and differential fin width

ABSTRACT

Methods for forming fins with a straight profile by preventing fin bending during STI fill and annealing are disclosed. Embodiments include providing STI regions separated by Si regions, each topped with a hardmask; planarizing the STI regions; removing the hardmask over a portion of the Si regions, forming recesses; forming a conformal spacer layer over the STI regions and in the recesses; removing horizontal portions of the spacer layer; epitaxially growing Si in each recess, forming fins; and etching the STI regions and a remainder of the spacer layer down to the Si regions to reveal the fins.

RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.15/348,109, filed Nov. 10, 2016, entitled “SPACER DEFINED FIN GROWTH ANDDIFFERENTIAL FIN WIDTH,” which is incorporated herein by reference inits entirety.

TECHNICAL FIELD

The present disclosure relates to the manufacture of semiconductordevices, such as integrated circuits (ICs). The present disclosure isparticularly applicable to forming and shaping fins, particularly forthe 7 nanometer (nm) technology node and beyond.

BACKGROUND

Narrow fins (i.e., having a width of 6 to 8 nanometers (nm)) aresusceptible to fin bending during the current shallow trench isolation(STI) oxide fill and anneal processes. Also, the current fin shapingprocess results in 7 nm fins having an undesirably tapered profile, andthere is no available solution to create straight fins having such anarrow width.

A need therefore exists for methodology enabling formation of a straightfin profile and the resulting device.

SUMMARY

An aspect of the present disclosure is to form fins having a straightprofile and uniform narrow width.

Another aspect of the present disclosure is to form fins having astraight profile and differential widths.

Another aspect of the present disclosure is a device having fins formedwith a straight profile and a uniform narrow width.

A further aspect of the present disclosure is a device having finsformed with a straight profile and differential widths.

Additional aspects and other features of the present disclosure will beset forth in the description which follows and in part will be apparentto those having ordinary skill in the art upon examination of thefollowing or may be learned from the practice of the present disclosure.The advantages of the present disclosure may be realized and obtained asparticularly pointed out in the appended claims.

According to the present disclosure, some technical effects may beachieved in part by a method including: providing STI regions separatedby silicon (Si) regions, each topped with a hardmask; planarizing theSTI regions; removing the hardmask over a portion of the Si regions,forming recesses; forming a conformal spacer layer over the STI regionsand in the recesses; removing horizontal portions of the spacer layer;epitaxially growing Si in each recess, forming fins; and etching the STIregions and a remainder of the spacer layer down to the Si regions toreveal the fins.

Aspects of the present disclosure include planarizing the STI regions bychemical mechanical polishing (CMP). Another aspect includes thehardmask including silicon nitride (SiN). A further aspect includes theportion of the Si regions forming NFET and PFET regions. Other aspectsinclude the hardmask having a width of 5 nm to 25 nm and a thickness of20 nm to 60 nm. Another aspect includes forming the spacer layer to athickness of 3 nm to 8 nm.

Another aspect include forming a mask over a second portion of the Siregions prior to removing the hardmask over the first portion of the Siregions; removing the mask over the second portion of the Si regionssubsequent to removing the horizontal portions of the spacer layer,forming second recesses; epitaxially growing Si in the second recessesconcurrently with epitaxially growing Si in the first recesses to formsecond fins; and etching the STI regions and a remainder of the spacerlayer to reveal the first fins and the second fins. A further aspectincludes the first portion of the Si regions forming portions of core(SG) devices and the second portion of the Si regions forming portionsof input/output (EG) devices. Other aspects include the hardmaskincluding SiN. Another aspect includes the hardmask having a width of 5nm to 25 nm and a thickness of 20 nm to 60 nm. A further aspect includesforming the spacer layer to a thickness of 3 nm to 8 nm.

Another aspect of the present disclosure is a device including: a Sisubstrate; STI regions formed in the Si substrate; and epitaxially grownSi fins with uniform width formed on the Si substrate, between the STIregions, wherein the width of each fin is less than a distance betweenadjacent STI regions. Another aspect of the device includes each finhaving a width of 2 nm to 17 nm, and the distance between adjacent STIregions is 5 nm to 25 nm. Other aspects include the epitaxially grown Sifins forming NFET and PFET regions.

A further aspect of the present disclosure is a device including: a Sisubstrate; STI regions formed in the Si substrate; and first epitaxiallygrown Si fins on a first portion of the Si substrate and secondepitaxially grown Si fins on a second portion of the Si substrate,wherein a width of each first epitaxially grown Si fin is less than awidth of each second epitaxially grown Si fin. Another aspect of thedevice includes each first epitaxially grown Si fin having a width of 5nm to 12 nm. Further aspects include each second epitaxially grown Sifin having a width of 8 nm to 25 nm. Other aspects include each secondepitaxially grown Si fin having a width equal to a distance betweenadjacent STI regions. Further aspects include the first epitaxiallygrown Si fins forming portions of core (SG) devices and the secondepitaxially grown Si fins forming portions of input/output (EG) devices.

Additional aspects and technical effects of the present disclosure willbecome readily apparent to those skilled in the art from the followingdetailed description wherein embodiments of the present disclosure aredescribed simply by way of illustration of the best mode contemplated tocarry out the present disclosure. As will be realized, the presentdisclosure is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects, all without departing from the present disclosure.Accordingly, the drawings and description are to be regarded asillustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawing and in whichlike reference numerals refer to similar elements and in which:

FIGS. 1A through 1F schematically illustrate a process flow for formingfins with a straight profile and uniform width, in accordance with anexemplary embodiment; and

FIGS. 2A through 2J schematically illustrate a process flow for formingSG fins and EG fins having differential widths and a straight profile,in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of exemplary embodiments. It should be apparent, however,that exemplary embodiments may be practiced without these specificdetails or with an equivalent arrangement. In other instances,well-known structures and devices are shown in block diagram form inorder to avoid unnecessarily obscuring exemplary embodiments. Inaddition, unless otherwise indicated, all numbers expressing quantities,ratios, and numerical properties of ingredients, reaction conditions,and so forth used in the specification and claims are to be understoodas being modified in all instances by the term “about.”

The present disclosure addresses and solves the current problem of finbending attendant upon STI oxide fill and anneal processes. Inaccordance with embodiments of the present disclosure, the SiN hardmaskis removed directly after STI CMP, thereby skipping the current STIdeglaze process. The removal of the SiN hardmask forms an STI oxidedefined trench for the fins. Spacers are formed on the sidewalls of thetrench, and fins are grown in the reduced width trenches. As a result,narrow fins can be formed with a straight profile.

Methodology in accordance with embodiments of the present disclosureincludes providing STI regions separated by Si regions, each topped witha hardmask. The hardmask over at least a portion of the Si regions isremoved, forming recesses, and a conformal spacer layer is formed overthe STI regions and in the recesses. Then, horizontal portions of thespacer layer are removed, and Si is epitaxially grown in each recess,forming fins. Subsequently, the STI regions and a remainder of thespacer layer are etched down to the Si regions to reveal the fins.

Still other aspects, features, and technical effects will be readilyapparent to those skilled in this art from the following detaileddescription, wherein preferred embodiments are shown and described,simply by way of illustration of the best mode contemplated. Thedisclosure is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects. Accordingly, the drawings and description are to be regardedas illustrative in nature, and not as restrictive.

FIGS. 1A through 1F schematically illustrate a process flow for formingfins with a straight profile and uniform width, in accordance with anexemplary embodiment. Adverting to FIG. 1A, after STI CMP, STI regions101 are separated by Si regions 103, each topped with a hardmask 105.The hardmask 105 is formed of SiN. The hardmask 105 has a width of 5 nmto 25 nm, defined by the fin pitch/width, and a thickness of 20 nm to 60nm, depending on the patterning stack requirement. Next, as illustratedin FIG. 1B, the hardmask 105 over each of the Si regions 103 is removed,forming recesses 107. The hardmask 105 can be removed by any SiN removalprocess selective to oxide, for example, a dry etch or a H₃PO₄ etch. TheSi regions 103 form NFET and PFET regions. Subsequently, a conformalspacer layer 109 is formed over the STI regions 101 and in the recesses107 by atomic layer deposition (ALD) or in-situ radical assisteddeposition (iRAD), as depicted in FIG. 1C. The spacer layer 109 isformed to a thickness of 3 nm to 8 nm, dependent on the desired amountof fin reduction. Then, as illustrated in FIG. 1D, horizontal portionsof the spacer layer 109 are removed by a dry etch. The dry etch isanisotropic to preserve the sidewall thickness while removing thehorizontal portions of the spacer layer 109. Next, Si is epitaxiallygrown in each recess 107 to form fins 111, as depicted in FIG. 1E. Asillustrated in FIG. 1F, the STI regions 101 and a remainder of thespacer layer 109 are then etched down to the Si regions 103 by wetetching with HF, dry etching, SiCoNi™ etching, or a chemical oxideremoval (COR) process to reveal the fins 111.

FIGS. 2A through 2J schematically illustrate a process flow for formingfins having differential widths and a straight profile, in accordancewith an exemplary embodiment. Adverting to FIG. 2A, after STI CMP, STIregions 201 are separated by Si regions 203, each topped with a hardmask205, similar to the embodiment of FIGS. 1A through 1F. The hardmask 205is formed of SiN. The hardmask 205 has a width of 5 nm to 25 nm, definedby the fin pitch/width, and a thickness of 20 nm to 60 nm, depending onthe patterning stack requirement. Next an oxide mask 207 is depositedover the STI regions 201 and hardmasks 205, as illustrated in FIG. 2B.The Si regions and intervening STI regions are divided into two areas, afirst device area, for example a core (SG) device area, and a seconddevice area, for example an input/output (EG) device area. A photoresistis formed over the second device area, as illustrated in FIG. 2C, andthe oxide mask 207 over the first device area is removed, as shown inFIG. 2D. The oxide mask 207 is deposited to a thickness of 3 nm to 5 nmby chemical vapor deposition (CVD) or high temperature oxidation (HTO)and is removed by etching, e.g. dry etching. Once the oxide mask 207 isremoved from the first device area, the photoresist 209 is also removed.Subsequently, as illustrated in FIG. 2E, the hardmask 205 is removed byany SiN removal process selective to oxide, for example, a dry etch or aH₃PO₄ etch, forming recesses 211 between the STI regions 205 in thefirst device area. Then, a spacer layer 213 having a thickness of 3 nmto 5 nm is conformally formed over the STI regions 201 and in therecesses 211 in the first device area, as depicted in FIG. 2F. Asillustrated in FIG. 2G, horizontal portions of the spacer layer 213 andthe remainder of oxide mask 207 are removed by a dry etch. Then, in FIG.2H, the hardmasks 205 in the EG device area are removed, formingrecesses 215. As illustrated in FIG. 2I, Si is epitaxially grownconcurrently in the recesses 211 and 215 to form fins 217 and fins 219,respectively. The fins 217 may have a width of 5 nm to 12 nm (e.g. forSG fins), and the fins 219 may have a width of 8 nm to 25 nm (e.g. forEG fins). Then, as illustrated in FIG. 2J, the STI regions 201 and aremainder of the spacer layer 213 are etched to reveal the fins 217 andfins 219.

The embodiments of the present disclosure can achieve several technicaleffects, such as preventing fin bending during STI fill and annealing,and forming fins with a straight profile either with a uniform narrowwidth or with differential widths. Devices formed in accordance withembodiments of the present disclosure enjoy utility in variousindustrial applications, e.g., microprocessors, smart phones, mobilephones, cellular handsets, set-top boxes, DVD recorders and players,automotive navigation, printers and peripherals, networking and telecomequipment, gaming systems, and digital cameras. The present disclosureenjoys industrial applicability in any of various types of highlyintegrated finFET semiconductor devices, particularly for the 7 nmtechnology node and beyond.

In the preceding description, the present disclosure is described withreference to specifically exemplary embodiments thereof. It will,however, be evident that various modifications and changes may be madethereto without departing from the broader spirit and scope of thepresent disclosure, as set forth in the claims. The specification anddrawings are, accordingly, to be regarded as illustrative and not asrestrictive. It is understood that the present disclosure is capable ofusing various other combinations and embodiments and is capable of anychanges or modifications within the scope of the inventive concept asexpressed herein.

What is claimed is:
 1. A device comprising: a silicon (Si) substrate;shallow trench isolation (STI) regions formed in the Si substrate; and afirst set of epitaxially grown Si fins with uniform width between theSTI regions on a first portion of the Si substrate and a second set ofepitaxially grown Si fins with uniform width between the STI regions ona second portion of the Si substrate.
 2. The device according to claim1, wherein the width of each of the first set of epitaxially grown Sifins is less than a distance between adjacent STI regions.
 3. The deviceaccording to claim 1, wherein the width of each of the first set ofepitaxially grown Si fins is less than a width of each of the second setof epitaxially grown Si fins.
 4. The device according to claim 2,wherein the distance between the adjacent STI regions is 5 nanometer(nm) to 25 nm.
 5. The device according to claim 1, wherein the width ofeach of the first set of epitaxially grown Si fins is 2 nm to 17 nm. 6.The device according to claim 1, wherein the width of each of the secondset of epitaxially grown Si fins is 8 nm to 25 nm.
 7. The deviceaccording to claim 1, wherein the width of each of the second set ofepitaxially grown Si fins is equal to a distance between adjacent STIregions on the second portion of the Si substrate.
 8. The deviceaccording to claim 1, wherein the first set of epitaxially grown Si finsform NFET and PFET regions.
 9. The device according to claim 1, whereinthe first set of epitaxially grown Si fins form portions of core (SG)devices.
 10. The device according to claim 1, wherein the second set ofepitaxially grown Si fins form portions of input/output (EG) devices.11. A device comprising: a silicon (Si) substrate; shallow trenchisolation (STI) regions formed in the Si substrate; and epitaxiallygrown Si fins with uniform width formed on the Si substrate, between theSTI regions, wherein the width of each fin is less than a distancebetween adjacent STI regions.
 12. The device according to claim 11,wherein the width of each of the epitaxially grown Si fins is 2nanometer (nm) to 17 nm.
 13. The device according to claim 11, whereinthe distance between the adjacent STI regions is 5 nm to 25 nm.
 14. Thedevice according to claim 11, wherein the epitaxially grown Si fins formNFET and PFET regions.
 15. A device comprising: a silicon (Si)substrate; shallow trench isolation (STI) regions formed in the Sisubstrate; and a first set of epitaxially grown Si fins on a firstportion of the Si substrate and a second set of epitaxially grown Sifins on a second portion of the Si substrate, wherein width of each ofthe first set of epitaxially grown Si fins is less than width of each ofthe second set of epitaxially grown Si fins.
 16. The device according toclaim 15, wherein each of the first set of epitaxially grown Si fins hasa width of 5 nm to 12 nm.
 17. The device according to claim 15, whereineach of the second set of epitaxially grown Si fins has a width of 8 nmto 25 nm.
 18. The device according to claim 15, wherein each of thesecond set of epitaxially grown Si fins has a width equal to a distancebetween adjacent STI regions.
 19. The device according to claim 15,wherein the first set of epitaxially grown Si fins form portions of core(SG) devices and the second set of epitaxially grown Si fins formportions of input/output (EG) devices.